The uvm_root class serves as the implicit top-level and phase controller for all UVM components. Users do not directly instantiate uvm_root. The UVM automatically creates a single instance of uvm_root that users can access via the global (uvm_pkg-scope) variable, uvm_top.
(see uvm_ref_root.gif)
The uvm_top instance of uvm_root plays several key roles in the UVM.
| Implicit top-level | The uvm_top serves as an implicit top-level component. Any component whose parent is specified as null becomes a child of uvm_top. Thus, all UVM components in simulation are descendants of uvm_top. |
| Phase control | uvm_top manages the phasing for all components. |
| Search | Use uvm_top to search for components based on their hierarchical name. See find and find_all. |
| Report configuration | Use uvm_top to globally configure report verbosity, log files, and actions. For example, uvm_top.set_report_verbosity_level_hier(UVM_FULL) would set full verbosity for all components in simulation. |
| Global reporter | Because uvm_top is globally accessible (in uvm_pkg scope), UVM’s reporting mechanism is accessible from anywhere outside uvm_component, such as in modules and sequences. See uvm_report_error, uvm_report_warning, and other global methods. |
The uvm_top instance checks during the end_of_elaboration phase if any errors have been generated so far. If errors are found a UVM_FATAL error is being generated as result so that the simulation will not continue to the start_of_simulation_phase.
class uvm_root extends uvm_component
Implementation of the uvm_root class, as defined in 1800.2-2017 Section F.7
| uvm_root | ||||||
| Class Hierarchy | ||||||
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| Class Declaration | ||||||
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| get() | Static accessor for uvm_root. | |||||
| Simulation Control | ||||||
| run_test | Phases all components through all registered phases. | |||||
| die | This method is called by the report server if a report reaches the maximum quit count or has a UVM_EXIT action associated with it, e.g., as with fatal errors. | |||||
| set_timeout | Specifies the timeout for the simulation. | |||||
| finish_on_completion | If set, then run_test will call $finish after all phases are executed. | |||||
| get_finish_on_completion | ||||||
| set_finish_on_completion | ||||||
| Topology | ||||||
| top_levels | This variable is a list of all of the top level components in UVM. | |||||
| find | ||||||
| find_all | Returns the component handle (find) or list of components handles (find_all) matching a given string. | |||||
| print_topology | Print the verification environment’s component topology. | |||||
| enable_print_topology | If set, then the entire testbench topology is printed just after completion of the end_of_elaboration phase. | |||||
| set_enable_print_topology | ||||||
| get_enable_print_topology | ||||||
static function uvm_root get()
Static accessor for uvm_root.
The static accessor is provided as a convenience wrapper around retrieving the root via the <uvm_coreservice_t::get_root> method.
// Using the uvm_coreservice_t: uvm_coreservice_t cs; uvm_root r; cs = uvm_coreservice_t::get(); r = cs.get_root(); // Not using the uvm_coreservice_t: uvm_root r; r = uvm_root::get();
virtual task run_test ( string test_name = "" )
Phases all components through all registered phases. If the optional test_name argument is provided, or if a command-line plusarg, +UVM_TESTNAME=TEST_NAME, is found, then the specified component is created just prior to phasing. The test may contain new verification components or the entire testbench, in which case the test and testbench can be chosen from the command line without forcing recompilation. If the global (package) variable, finish_on_completion, is set, then $finish is called after phasing completes.
virtual function void die()
This method is called by the report server if a report reaches the maximum quit count or has a UVM_EXIT action associated with it, e.g., as with fatal errors.
Calls the uvm_component::pre_abort() method on the entire uvm_component hierarchy in a bottom-up fashion. It then calls uvm_report_server::report_summarize and terminates the simulation with $finish.
function void set_timeout( time timeout, bit overridable = 1 )
Specifies the timeout for the simulation. Default is `UVM_DEFAULT_TIMEOUT
The timeout is simply the maximum absolute simulation time allowed before a FATAL occurs. If the timeout is set to 20ns, then the simulation must end before 20ns, or a FATAL timeout will occur.
This is provided so that the user can prevent the simulation from potentially consuming too many resources (Disk, Memory, CPU, etc) when the testbench is essentially hung.
`ifdef UVM_ENABLE_DEPRECATED_API bit finish_on_completion = 1
If set, then run_test will call $finish after all phases are executed.
virtual function bit get_finish_on_completion()
virtual function void set_finish_on_completion( bit f )
uvm_component top_levels[$]
This variable is a list of all of the top level components in UVM. It includes the uvm_test_top component that is created by run_test as well as any other top level components that have been instantiated anywhere in the hierarchy.
function uvm_component find ( string comp_match )
function void find_all ( string comp_match, ref uvm_component comps[$], input uvm_component comp = null )
Returns the component handle (find) or list of components handles (find_all) matching a given string. The string may contain the wildcards,
function void print_topology ( uvm_printer printer = null )
Print the verification environment’s component topology. The printer is a uvm_printer object that controls the format of the topology printout; a null printer prints with the default output.
bit enable_print_topology = 0
If set, then the entire testbench topology is printed just after completion of the end_of_elaboration phase.
function void set_enable_print_topology ( bit enable )
function void set_enable_print_topology (bit enable)
Sets the variable to enable printing the entire testbench topology just after completion of the end_of_elaboration phase.
@uvm-accellera The details of this API are specific to the Accellera implementation, and are not being considered for contribution to 1800.2
function bit get_enable_print_topology ()
function bit get_enable_print_topology()
Gets the variable to enable printing the entire testbench topology just after completion.
@uvm-accellera The details of this API are specific to the Accellera implementation, and are not being considered for contribution to 1800.2
The uvm_void class is the base class for all UVM classes.
virtual class uvm_void
The uvm_object class is the base class for all UVM data and hierarchical classes.
virtual class uvm_object extends uvm_void
The uvm_report_object provides an interface to the UVM reporting facility.
class uvm_report_object extends uvm_object
The library implements the following public API beyond what is documented in 1800.2.
virtual class uvm_component extends uvm_report_object
class uvm_root extends uvm_component
function uvm_component find ( string comp_match )
Returns the component handle (find) or list of components handles (find_all) matching a given string.
function void find_all ( string comp_match, ref uvm_component comps[$], input uvm_component comp = null )
function void uvm_report_error( string id, string message, int verbosity = UVM_NONE, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0 )
function void uvm_report_warning( string id, string message, int verbosity = UVM_MEDIUM, string filename = "", int line = 0, string context_name = "", bit report_enabled_checked = 0 )
Static accessor for uvm_root.
static function uvm_root get()
Phases all components through all registered phases.
virtual task run_test ( string test_name = "" )
This method is called by the report server if a report reaches the maximum quit count or has a UVM_EXIT action associated with it, e.g., as with fatal errors.
virtual function void die()
Specifies the timeout for the simulation.
function void set_timeout( time timeout, bit overridable = 1 )
If set, then run_test will call $finish after all phases are executed.
`ifdef UVM_ENABLE_DEPRECATED_API bit finish_on_completion = 1
virtual function bit get_finish_on_completion()
virtual function void set_finish_on_completion( bit f )
This variable is a list of all of the top level components in UVM.
uvm_component top_levels[$]
Print the verification environment’s component topology.
function void print_topology ( uvm_printer printer = null )
If set, then the entire testbench topology is printed just after completion of the end_of_elaboration phase.
bit enable_print_topology = 0
function void set_enable_print_topology ( bit enable )
function bit get_enable_print_topology ()
This callback is executed when the message system is executing a UVM_EXIT action.
virtual function void pre_abort
Outputs statistical information on the reports issued by this central report server.
pure virtual function void report_summarize( UVM_FILE file = UVM_STDOUT )