Register Sequence Classes

UVMkit » 1800.2-2017

This section defines the base classes used for register stimulus generation.

Summary
Register Sequence Classes
This section defines the base classes used for register stimulus generation.

uvm_reg_sequence

This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”.

  • When used as a base for user-defined RegModel test sequences, this class provides convenience methods for reading and writing registers and memories.  Users implement the body() method to interact directly with the RegModel model (held in the model property) or indirectly via the delegation methods in this class.
  • When used as a translation sequence, objects of this class are executed directly on a bus sequencer which are used in support of a layered sequencer use model, a pre-defined convert-and-execute algorithm is provided.

Register operations do not require extending this class if none of the above services are needed.  Register test sequences can be extend from the base uvm_sequence #(REQ,RSP) base class or even from outside a sequence.

Note- The convenience API not yet implemented.

Summary
uvm_reg_sequence
This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”.
Class Hierarchy
BASE
uvm_reg_sequence
Class Declaration
class uvm_reg_sequence #(
    type  BASE  =  uvm_sequence #(uvm_reg_item)
) extends BASE
BASESpecifies the sequence type to extend from.
modelBlock abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.
adapterAdapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.
reg_seqrLayered upstream “register” sequencer.
Convenience Write/ Read APIThe following methods delegate to the corresponding method in the register or memory element.
rw_infoHolds information about the register being read or written
sequencerSequencer executing the operation

BASE

Specifies the sequence type to extend from.

When used as a translation sequence running on a bus sequencer, BASE must be compatible with the sequence type expected by the bus sequencer.

When used as a test sequence running on a particular sequencer, BASE must be compatible with the sequence type expected by that sequencer.

When used as a virtual test sequence without a sequencer, BASE does not need to be specified, i.e. the default specialization is adequate.

To maximize opportunities for reuse, user-defined RegModel sequences should “promote” the BASE parameter.

class my_reg_sequence #(type BASE=uvm_sequence #(uvm_reg_item))
                              extends uvm_reg_sequence #(BASE);

This way, the RegModel sequence can be extended from user-defined base sequences.

model

uvm_reg_block model

Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.

adapter

uvm_reg_adapter adapter

Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.

reg_seqr

uvm_sequencer #( uvm_reg_item ) reg_seqr

Layered upstream “register” sequencer.

Specifies the upstream sequencer between abstract register transactions and physical bus transactions.  Defined only when this sequence is a translation sequence, and we want to “pull” from an upstream sequencer.

Convenience Write/ Read API

The following methods delegate to the corresponding method in the register or memory element.  They allow a sequence body() to do reads and writes without having to explicitly supply itself to parent sequence argument.  Thus, a register write

model.regA.write(status, value, .parent(this));

can be written instead as

write_reg(model.regA, status, value);

rw_info

uvm_reg_item rw_info

Holds information about the register being read or written

sequencer

uvm_sequencer_base sequencer

Sequencer executing the operation

class uvm_reg_sequence #( type  BASE  =  uvm_sequence #(uvm_reg_item) ) extends BASE
This class provides base functionality for both user-defined RegModel test sequences and “register translation sequences”.
uvm_reg_block model
Block abstraction this sequence executes on, defined only when this sequence is a user-defined test sequence.
uvm_reg_adapter adapter
Adapter to use for translating between abstract register transactions and physical bus transactions, defined only when this sequence is a translation sequence.
uvm_sequencer #( uvm_reg_item ) reg_seqr
Layered upstream “register” sequencer.
uvm_reg_item rw_info
Holds information about the register being read or written
uvm_sequencer_base sequencer
Sequencer executing the operation
virtual class uvm_sequence #(
    type  REQ  =  uvm_sequence_item,
    type  RSP  =  REQ
) extends uvm_sequence_base
The uvm_sequence class provides the interfaces necessary in order to create streams of sequence items and/or other sequences.