Base class for user-defined back-door register and memory access.
This class can be extended by users to provide user-specific back-door access to registers and memories that are not implemented in pure SystemVerilog or that are not accessible using the default DPI backdoor mechanism.
uvm_reg_backdoor | ||||
Base class for user-defined back-door register and memory access. | ||||
Class Hierarchy | ||||
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Class Declaration | ||||
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The uvm_void class is the base class for all UVM classes.
virtual class uvm_void
The uvm_object class is the base class for all UVM data and hierarchical classes.
virtual class uvm_object extends uvm_void
Base class for user-defined back-door register and memory access.
virtual class uvm_reg_backdoor extends uvm_object